1. Field of the Invention
This invention relates to electronic interface control circuitry and, more particularly, to circuitry for controlling the bipolar buffers of MOS peripheral devices in a microcomputer system.
2. Description of the Prior Art
In a microcomputer system there is typically a central processing unit (CPU), memory, and various peripheral devices for handling specific functions, such as the input/output functions of the system and direct memory access operations. These various units of the system typically communicate with each other in a bus organization. Such an organization of a microcomputer system 2 is illustrated in FIG. 1. One exemplary system could be an IBM AT desktop computer programmed to operate with an Am8052 cathode ray tube controller peripheral. A CPU 10 communicates with its peripheral devices 11, 12 and its memory unit 13 by the buses 14, 15. The buses 14, 15 are shown separately to illustrate a typical microcomputer bus organization in which the data signals are exchanged on one set of signal lines 14 while the control signals are exchanged on another set of signal lines 15.
In many, if not most, microcomputer systems 2 address signals are also communicated in the data bus 14. Thus the terms "data" or "data signals" also refer to "address" or "address signals," unless otherwise indicated.
The devices in present-day microcomputer systems 2 are typically in the form of MOS integrated circuits. MOS technology permits a higher degree of integration than bipolar technology. However, a drawback of MOS devices is that these devices are inherently unsuited for driving heavy loads, such as a microcomputer bus system.
A standard practice is to insert a bipolar buffer or transceiver circuit between the MOS device and the system buses. The buffers, having bipolar transistors, are much more capable of driving signals between the various devices of the microcomputer system. Thus the operation of the buffer is to acept a signal from its peripheral device and to generate a corresponding signal more suitable for the bus organization. Similarly, the buffer accepts signals from the bus, which may be weak, and boosts these signals for its peripheral device to receive.
However, a problem arises when the peripheral unit can operate in a "master/slave" mode. In a simple microcomputer system the CPU is the master, or initiator of operations, of the system. By control signals on the control system bus, the CPU can request data from other units which are in slave modes, or respondants to the master, for processing by the CPU. The CPU can also transfer the data to other units.
In the more sophisticated systems one of the peripheral units may also become the master of the system when the CPU relinquishes control. After the peripheral has performed its tasks, it releases control to permit the CPU to reassert itself as master, and the peripheral returns to its slave mode by which it responds to commands from the system master.
There is a problem for such a peripheral capable of operating in the master and slave modes. The device in one mode may transmit and receive data; likewise, in the second mode the device also may transmit and receive data. This requires some control logic for the bipolar buffer in order that the data signals are properly transmitted to and received from the data bus of the system. Heretofore, additional logic typically in the form of SSI (small scale integration) integrated circuits have been used to control the bipolar buffer.
Such a prior art arrangement is illustrated in FIG. 2. A bipolar buffer circuit 17 sends and receives control signals on the control signal bus path 14. Data signals are passed to and from the data bus 15. These control and data signals are relayed to a master/slave peripheral unit 20. Data signals pass directly to and from the peripheral 20 on the bipolar buffer 17. On the other hand, the control signal path is interrupted by a logic unit 16 which communicates to the peripheral 20 by a signal path 18 and to the bipolar buffer 17 by the path 19. The operation of the logic block 16 is such that upon receiving signals from the peripheral 20 from and to the path 18, the block 16 determines whether data signals will be transmitted or received by the peripheral unit 20 and accordingly sends control signals on the path 19 to the buffer unit 17 to properly enable the circuits within the unit 17 to drive the data signals between the paths 15, 23. The logic unit 16 also simultaneously allows control signals to pass along the paths 14, 18, 19 through the buffer unit 17 for the reception and transmission of control signals.
An object of the present invention is toward eliminating the logic block 16 so that a reduction in costs in the microcomputer system may be realized. No costs for the design for such a unit 16 need be incurred, and purchases of these additional SSI devices are avoided. The system is also simplified by the elimination of an additional part.
Another object of the present invention is to improve the performance of the buffer circuit by increasing its operating speed. In some cases, the response time of the buffer unit 17 is increased to speed the operations of the system.